1. Field of the Invention
The present invention relates to an electrically writable/erasable non-volatile semiconductor memory device, and an information apparatus using the same. More particularly, the present invention relates to a non-volatile semiconductor memory device which electrically executes data read, write and erase operations separately, such as flash EEPROM (flash memory), and the like, and an information apparatus using the same.
2. Description of the Related Art
In conventional electrically writable/erasable flash memories, the electrode voltage of each selected transistor in memory cells subjected to a data write/erase operation is in a write/erase mode in which the voltage is suited to the write/erase operation. In memory cells subjected to an electrical read operation, the electrode voltage of each transistor in selected memory cells is in a read mode in which the voltage is suited to the read operation.
Typically, the write/erase mode and the read mode have to have a different applied electrode voltage. Therefore, it is difficult to allow memory cells in the write/erase mode and memory cells in the read mode to coexist in the same memory block. For this reason, dual work flash memories have been widely developed and used.
The dual work flash memory comprises a plurality of memory banks including some memory blocks. While one of a plurality of memory banks is subjected to a write/erase operation, a read operation is carried out for another memory bank, thereby achieving a so-called dual work operation.
In the dual work flash memory, the memory bank of the write/erase operation and the other memory bank of the read operation have to be controlled by separate address signals.
This is because an address signal input for the read operation has to avoid affecting the write/erase operation executed in the other memory bank. Therefore, the dual work flash memory has to have address signals on at least two lines (at least two sets of address signals).
An example of the address control of the dual work flash memory will be described with reference to FIG. 9 which shows major portions of the dual work flash memory.
In FIG. 9, the dual work flash memory has input buffer 21, an address control circuit 22, a command recognition section 23, a write/erase control circuit 24, two memory banks a and b, a decoder circuit 25 connected to memory bank a, and a decoder circuit 26 connected to memory bank b.
An address signal A is input to the input buffer 21 from an external address pad (not shown).
An address signal Abuf is input to the address control circuit 22 from the input buffer 21.
A command signal C is input to the command recognition section 23. When the command recognition section 23 recognizes the signal as a valid command, the command recognition section 23 outputs a latch control signal Clatch to the address control circuit 22, and a control signal Cwsm identifying the type of the command from the command recognition section 23 to the write/erase control circuit 24.
To the write/erase control circuit 24, a bank signal Cbank1 described below is input from the address control circuit 22, and the control signal Cwsm is input from the command recognition section 23. The write/erase control circuit 24 outputs write/erase control signals Ca and Cb.
To the decoder circuit 25, an address signal Aa is input from the address control circuit 22, and the write/erase control signal Ca is input from the write/erase control circuit 24.
To the decoder circuit 26, an address signal Ab is input from the address control circuit 22, and the write/erase control signal Cb is input from the write/erase control circuit 24.
Hereinafter, the address control circuit 22 which outputs the address signals Aa and Ab which correspond to the above-described address signal on two lines will be described in detail with reference to FIG. 10.
As shown in FIG. 10, the address control circuit 22 has an address latch circuit 31 controlled by the latch control signal Clatch, a bank decoder 32 which decodes the received address signal Abuf so as to indicate which memory bank an address is directed to, a latch circuit 33 which is controlled by the latch control signal Clatch and stores a bank signal Cbank decoded by the bank decoder 32, and a multiplexer circuit 34 which is controlled by the bank signal Cbank1 stored by the latch circuit 33 and performs connection control so that an address signal Alatch latched by the address latch circuit 31 and the address signal Abuf correspond to the address signals Aa and Ab on the two lines. The bank signal Cbank1 is also output to the write/erase control circuit 24.
It should be noted that general flash memories further include a data signal carrying information to be written, a sense circuit for reading information stored in memory cells, various circuits for high voltage (hereinafter also referred to as a high-voltage-related circuit), such as a booster circuit and the like. These are not specifically involved in the present invention and therefore are not shown. The structure and operation of such elements are not described unless particularly required.
Hereinafter, for example, a description is given of address control when data is read from memory bank b while data is written to memory bank a.
When the dual work flash memory is instructed to write data to memory bank a, the command signal C represents a command of a write operation, and the address signal A represents an address in memory bank a.
The command signal C is recognized (identified) by the command recognition section 23 as a write command, and activates the latch control signal Clatch. Further, control signal Cwsm informs the write/erase control circuit 24 that the input command is a write command.
On the other hand, the input buffer 21 receives the address signal A and transfers the address signal Abuf to the address control circuit 22. The address control circuit 22 receives the activated latch control signal Clatch from the command recognition section 23, and causes the address signal Abuf to be stored in the address latch circuit 31.
Further, the bank decoder 32 decodes the input address signal Abuf so as to indicate which bank the address represented by the input address signal Abuf is directed to (i.e., whether the address is in memory bank a or memory bank b). Assuming that memory banks a and b have the same memory capacity (the size of address space), and a memory map as shown in FIG. 11, the address signal Abuf designates memory bank a when the most significant bit of the address is xe2x80x9c0xe2x80x9d, while the address signal Abuf designates memory bank b when the most significant bit of the address is xe2x80x9c1xe2x80x9d.
The bank signal Cbank decoded by the bank decoder 32 is stored in the latch circuit 33 in response to the activation of the latch control signal Clatch.
Further, based on the bank signal Cbank1 stored by the latch circuit 33, the multiplexer circuit 34 performs connection control so that the address signal Alatch stored in the address latch circuit 31 and address signal Abuf correspond to the respective address signals Aa and Ab.
The above-described operations connect signal lines so that the address signal Alatch stored in the address latch circuit 31 corresponds to the address signal Aa directed to memory bank a, while the address signal Abuf output from the input buffer 21 corresponds to the address signal Ab directed to memory bank b.
The write/erase control circuit 24 receives the bank signal Cbank1, activates the write/erase control signal Ca directed to memory bank a, and controls the decoder circuit 25 so that memory cells selected by the address signal Aa in memory bank a are caused to be in the write mode.
The address signal Ab to memory bank b is logically and electrically separated from the address signal Aa to memory bank a by the multiplexer circuit 34 in the address control circuit 22. The address signal Ab is also connected to correspond to the address signal Abuf from the input buffer 21. In this situation, when a request for a read operation which designates an address is externally input, memory cells in memory bank b are arbitrarily selected irrespective of an address selected in memory bank a.
It should be noted that although memory banks a and b have the same size for the sake of simplicity, even when memory banks a and b have a different size, the same function can be achieved by modifying the logic of the bank decoder 32. The same function can also be obtained when a read operation is carried out in memory bank a while a write/erase operation is carried out in memory bank b. In this case, in the multiplexer circuit 34, signal lines are connected so that the address signal Abuf output by the input buffer 21 corresponds to the address signal Aa directed to memory bank a, while the address signal Alatch stored in the address latch circuit 31 correspond to the address signal Ab directed to memory bank b.
Generally, the dual work flash memory is often employed in portable apparatuses in which an area occupied by a memory device is limited. Hereinafter, a representative system example of a portable apparatus using the dual work flash memory will be described with reference to FIG. 12 as to the usage and necessity of the dual work flash memory in the portable apparatus.
As shown in FIG. 12, the system of the portable apparatus has a CPU 51 for controlling the entire portable apparatus, a dual work flash memory 52, a RAM 53, an I/O interface 54 for controlling an I/O apparatus such as a microphone, a liquid crystal display apparatus or the like, and a data bus 55 for connecting communicably and electrically these elements.
The CPU 51 typically executes an executable code (instruction code) stored in the dual work flash memory 52. FIG. 12 is referenced for the purpose of describing an operation of the dual work flash memory, and does not show other devices, control signals, or the like.
For example, an operation in which audio data input from a microphone as an input apparatus is stored in the dual work flash memory 52 will be considered below.
In this case, the CPU 51 has to execute the instruction code so to control the dual work flash memory 52 and the I/O interface 54. Since the code is stored in the dual work flash memory 52 as described above, the CPU 52 has to fetch the code from the dual work flash memory 52 via a path (1) on the data bus 55.
In order to store the audio data to the dual work flash memory 52 via the I/O interface 54, data has to be transferred via a path (2) on the data bus 55.
If a flash memory which does not have a dual work function is employed, the fetch of the code via path (1) cannot be carried out when data obtained via path (2) is being written to the flash memory 52. In other words, the CPU 51 cannot work when data is being written into the flash memory 52. Similarly, the CPU 51 cannot work when data is being erased from the flash memory 52.
Generally, in flash memories, a data write/erase speed is sufficiently slow compared to a data read speed so that an instantaneous response, important to portable apparatuses (information apparatuses), may be impaired. This problem may be solved by storing the instruction code in another flash memory or ROM. However, such a solution is not practical in consideration of the above-described limitation of the occupied area and the level of convenience when the instruction code is stored in the flash memory.
In such a system, use of the dual work flash memory makes it possible to achieve the fetch of codes via path (1) while data (audio data) is being stored via path (2) (write operation). In this case, the data and the codes have to be stored in separate memory banks.
A region in which codes for the CPU 51 are stored and read operations are mainly carried out is herein defined as a code region. A region in which various data is stored and write/erase operations are frequently carried out is herein defined as a data region. These are not the only definitions. As described above, in the forgoing example, the code region and the data region have to correspond to separate memory banks. For example, the code region corresponds to memory bank a, while the data region corresponds to memory bank b, and the like. Assuming that the dual work flash memory has two memory banks a and b having the same memory capacity, the data region and the code region have the same memory capacity.
The memory capacity ratio between the data region and the code region, which is required by the user, varies greatly according to an application in which they are employed. For example, for an application in which large-size data (image data or the like) is handled, the data region is larger. For an application having a number of functions, the code region has to have a large memory capacity. Particularly, the timing of when to determine the memory capacity of the code region is determined depends greatly on the quality or performance of a system program or an application program. Therefore, it is possible that the memory capacity ratio is changed after system hardware is completed.
These various demands are met by preparing a plurality of combinations of memory capacities of switchable memory banks. Assuming a dual work flash memory has a total capacity of 32M bits, there are combinations of 24 M and 8M (memory bank a has a capacity of 24 M while memory bank b has a capacity of 8 M), and 16 M and 16 M, and the like, for example. Some techniques are considered to realize a plurality of combinations on a single chip for the purpose of a reduction in development cost.
In one of such techniques, a decoder is provided on opposite ends of a memory array, and word lines and/or bit lines are separated (cut) at an appropriate position by a hard mask. Specifically, in a process of producing a semiconductor memory device, a wiring pattern is fixedly modified by changing a mask for forming wires. By changing a position which is to be cut using a hard mask, it is possible to divide the memory array into a plurality of regions having various memory capacity ratios (a plurality of memory banks).
With this technique, the same decoder circuits correspond to respective memory bank capacities generated by switching. This leads to an increase in chip area and a difficulty in optimizing an access time and the like. Further, the memory capacities cannot be changed after the completion of the chip, resulting in disadvantages, such as evaluation of the access time cannot be carried out in terms of a memory capacity ratio, the production takes a long time, and the like.
In another technique, a plurality of small-capacity memory banks are prepared, and some of the memory banks are appropriately combined so that the combination seemingly works as a memory bank. FIG. 13 shows an exemplary configuration of a dual work flash memory having four memory banks. For the sake of simple comparison with the above-described example, the capacities of memory banks a2 to d2 are half the capacities of the above-described memory banks a and b, respectively. In this case, the total capacity of memory banks a2 to d2 is the same as the total capacity of memory banks a and b. The components in FIG. 13 are similar to those in FIG. 9 and the description thereof is omitted here. Specifically, an input buffer 61 corresponds to the input buffer 21, a command recognition section 63 corresponds to a command recognition section 23, a write/erase control circuit 64 corresponds to the write/erase control circuit 24, and an address control circuit 62 corresponds to an address control circuit 22.
The address control circuit 62 outputs address signals Aa2 to Ad2 to the corresponding memory banks a2 to d2, which signals are input to decoders 65 to 68.
The write/erase control circuit 64 outputs write/erase control signals Ca2 to Cd2, which are similarly input to the respective decoders 65 to 68.
FIG. 14 is a diagram of a configuration of the address control circuit 62, showing major parts thereof. Except for a multiplexer circuit 74, the other components are similar to those in the address control circuit 22 of FIG. 10. Specifically, an address latch circuit 71 corresponds to the address latch circuit 31, a bank decoder 72 corresponds to the bank decoder 32, and a latch circuit 73 corresponds to a latch circuit 33. In this case, since there are four memory banks a2 to d2, the multiplexer circuit 74 and the bank decoder 72 additionally receives a control signal Cmux, and outputs address signals Aa2 to Ad2 directed to the respective memory banks a2 to d2.
In this configuration, there are three possible combinations of the memory capacities. Specifically, a combination of (a2) and (b2+c2+d2) provides a memory bank configuration having a memory capacity ratio of 1:3 where it is assumed that memory banks b2 to d2 constitute a single memory bank. Similarly, a combination of (a2+b2) and (a2+d2) provides a memory capacity ratio of 2:2 (1:1), and a combination of (a2+b2+c2) and (d2) provides a memory capacity ratio of 3:1. FIG. 15 shows the memory maps of these configurations.
In FIG. 15, it is assumed that an address value ascends in order of memory banks a2xe2x86x92b2xe2x86x92c2xe2x86x92d2. It is necessary that the multiplexer circuit 74 and the bank decoder 72 are informed using the control signal Cmux of which of the above-described three combinations of the memory banks are selected. For example, it is assumed that the 1:3 configuration is selected. The bank decoder 72 decodes an address signal Abuf to find whether the input address is included in memory bank a2 or any of (b2, c2, d2). The multiplexer circuit 74 has to separate Aa2 from (Ab2, Ac2, Ad2) by hardware. In this case, if each of the address signals (Ab2, Ac2, Ad2) is logically connected to the respective memory banks (i.e., the same address signal is transferred), control is made easier.
Operations other than those described above are similar to those in the address control circuit 22 of FIG. 10. The above-described configuration makes it possible to achieve a dual work flash memory which has a memory bank capacity ratio of 1:3, 1:1 and 3:1. It should be noted that if minute settings of the above-described memory capacity ratios are required, the capacity of each memory bank is made small and a larger number of memory banks are used.
To achieve the above-described dual work flash memory having a number of small-capacity memory banks, the number of address signals has to be the same as the number of the memory banks. For example, in the case of the dual work flash memory of FIG. 13 having the four memory banks a2 to d2, the four address signals Aa2 to Ad2 are required. Assuming that the flash memory has a total memory capacity of 32 M bits, the four memory bank a2 to d2 each have a memory capacity of 8 M bits. If access can be executed in units of a byte (8 bits), the bit width of an address corresponding to each memory bank requires at least 20 bits.
In this case, four sets of addresses having a bit width of at least 20 bits are required, and at least 80 address signal lines are provided. If each memory bank capacity is divided into halves and 8 memory banks are provided, 8 sets of addresses having a bit width of at least 19 bits are required, so that at least 152 address signal lines are provided.
Thus, if each memory bank is segmentized, the number of address signals is significantly increased. Further, the size of a high-voltage-related circuit, a sense circuit, a decoder circuit, and the like is increased, so that the proportion of the chip area occupied by a memory cell region (memory cell occupation ratio) is reduced. This leads to an increase in the chip area. In other words, this leads to an increase in manufacturing cost for the chip and a reduction in yield. Moreover, as the number of combinations of memory bank capacities is increased, the number of combinations of operation verifications indispensable for development is increased, leading to an increase in man-hours.
According to one aspect of the present invention, a non-volatile semiconductor memory device comprises a plurality of memory banks each including a plurality of memory cells, a command recognition section for identifying an externally input command signal and outputting an identification signal, an internal control section for generating a control signal for executing a command designated by the identification signal, an address control section for generating an internal address signal to a memory region including an arbitrary combination of the plurality of memory banks to be accessed, based on the externally input address signal, and a first address inversion section for inverting or non-inverting the logical values of at least a specific bit of the input address signal and outputting the resultant input address signal to the address control section. Predetermined memory cells are accessed based on the control signal and the internal address signal. Thereby, the above-described object is achieved.
According to another aspect of the present invention, a non-volatile semiconductor memory device comprises a plurality of memory banks each including a plurality of memory cells, a command recognition section for identifying an externally input command signal and outputting an identification signal, an internal control section for generating a control signal for executing a command designated by the identification signal, an address control section for generating an internal address signal to a memory region including an arbitrary combination of the plurality of memory banks to be accessed, based on the externally input address signal, and a second address inversion section for interchanging at least a specific bit of the input address signal with at least another specific bit thereof and outputting the resultant input address signal to the address control section. Predetermined memory cells are accessed based on the control signal and the internal address signal. Thereby, the above-described object is achieved. The interchange between one specific bit and another specific bit of an input address signal includes interchange of two consecutive specific bits (e.g., the two most significant bits), and interchange of any two specific bits.
In one embodiment of this invention, the first address inversion section comprises a logic inversion section for inverting the logical value of the address signal, and a first output switching section for switching between the same logic output of the address signal and an output of the logic inversion section.
In one embodiment of this invention, the second address inversion section comprises a second output switching section for interchanging at least a specific bit of the input address signal with at least another specific bit thereof.
In one embodiment of this invention, the first output switching section or the second output switching section switches outputs thereof using a wiring pattern provided in a production process of the device.
In one embodiment of this invention, the first output switching section or the second output switching section comprises a memory element capable of setting a state thereof, and a logic element for switching outputs thereof depending on the set state stored in the memory element.
In one embodiment of this invention, the first output switching section or the second output switching section comprises a logic element for switching outputs thereof depending on an externally input logical value.
In one embodiment of this invention, the memory capacity of the memory bank is xc2xdn of the capacity of the overall memories (e.g., the memory banks) where n is a natural number.
In one embodiment of this invention, the non-volatile semiconductor memory device is an electrically writable and erasable flash memory.
According to another aspect of the present invention, a non-volatile semiconductor memory device comprises a plurality of memory blocks each comprising a plurality of memory cells arranged in a matrix, and a plurality of memory banks comprising some of the plurality of memory blocks. The non-volatile semiconductor memory device further comprises an address inversion section for inverting a specific address signal. Therefore, the logical arrangement of the memory banks is made changeable. Thereby, the above-described object is achieved.
According to another aspect of this invention, an information apparatus comprises the above-described non-volatile semiconductor memory device. A memory operation is carried out using the non-volatile semiconductor memory device.
Hereinafter, functions of the present invention will be described. In the present invention, it is possible to invert a specific bit(s) of specific address signals or interchange it with another specific bit(s) to change the logical arrangement of memory banks without changing the physical arrangement of the memory banks. Specifically, by inverting or interchanging specific address signals, the combinations of memory banks having a memory capacity ratio of m:n and n:m (e.g., 1:2 and 2:1) can be obtained by the same internal operation. Therefore, the number of sets of address signals can be reducecd. Thereby, the non-volatile semiconductor memory device having a number of combinations of memory bank capacity ratios can be easily achieved without increasing the number of address signals and address signal lines, reducing a memory cell cccupation ratio, elongating a development time due to increased verification patterns, or the like.
Thus, the invention described herein makes possible the advantages of providing a non-volatile semiconductor memory device in which specific addresses are selectively inverted, or the like, so that the number of combinations of segmentized memory banks can be easily increased without leading to a significant increase in address signals and address signal lines; and an information apparatus using the same.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.